A CMOS image sensor is proposed which has a pixel array section provided as a plurality of pixels in a two dimensional alignment, sequentially reads out a pixel signal read from each pixel of the pixel array section for each of the pixel columns, performs CDS processing and the like on each column signal, and converts and outputs the image signals.
A column parallel output type of the CMOS image sensor, which has an FD amplifier having a floating diffusion (FD) layer for each pixel and in which the output thereof is performed by selecting one row from among the pixel arrays and reading out the selected row simultaneously in the column direction, is predominant.
This is because parallel processing is advantageous since it is difficult to obtain sufficient driving capacity in an FD amplifier arranged in the pixel and accordingly it is necessary to lower the data rate.
In regard to the pixel signal read out (output) circuit of the column parallel output type CMOS image sensor, in fact, various versions have been proposed.
One version which is the most advanced is a type where an analog-digital converter (abbreviated as ADC below) is provided for each column and a pixel signal is output as a digital signal.
A CMOS image sensor mounted with such a column parallel type ADC is, for example, disclosed by JP-A-2005-278135 and W. Yang et. al., “An Integrated 800×600 CMOS ImageSystem,” ISSC Digest of Technical Papers, pp. 304-305, February, 1999.
FIG. 1 is a block diagram illustrating a configuration example of a solid-state imaging element mounted with a column parallel ADC (CMOS image sensor).
As shown in FIG. 1, a solid-state imaging element 1 has a pixel section 2, a vertical scanning circuit 3, a horizontal transfer scanning circuit 4, and a column processing circuit group 5 formed from a group of ADCs.
In addition, the solid-state imaging element 1 has a digital-analog converter (abbreviated as DAC below) 6 and an amplifier circuit (S/A) 7.
The pixel section 2 is configured by a unit pixel 21, which includes a photo diode (photoelectric conversion element) and an inner-pixel amplifier, being arranged in a matrix shape (column-row shape).
In the column processing circuit group 5, a plurality of column processing circuits 51, which forms an ADC for each column, is column parallel.
Each of the column processing circuits (ADC) 51 has a comparator 51-1 which compares a reference signal RAMP (Vslop), which is a ramp waveform (RAMP) which changes a reference signal generated using a DAC6 into a stepwise shape, and an analog signal, which is obtained from pixels for each row via a vertical signal line.
Furthermore, each of the column processing circuits 51 counts the comparison time of the comparator 51-1 and has a counter latch 51-2 which holds the count result.
The column processing circuits 51 have an n bit digital signal conversion function and are arranged for each vertical signal line (column line) 8-1 to 8-n so as to configure a column parallel ADC block.
The output of each of a memory 51-2 is connected to, for example, a horizontal transfer line 9 with a k bit width.
In addition, k amplifier circuits 7 are arranged corresponding to the horizontal transfer lines 9.
FIG. 2 is a diagram illustrating a timing chart of a circuit of FIG. 1.
In each of the column processing circuits (ADC) 51, the analog signals (potential Vsl) read out from the vertical signal line 8 are compared by the comparator 51-1 arranged for each column to, for example, the reference signal RAMP (Vslop) changing into a stepwise shape.
At this time, the levels of the analog potential Vsl and the reference signal RAMP (Vslop) cross, and counting is performed by the counter latch 51-2 using a standard clock CK until the output of the comparator 51-1 is reversed. According to this, the potential (analog signal) Vsl of the vertical signal line 8 is converted to a digital signal (AD converted). At this time, the counter is configured as a down bit ripple counter.
The AD conversion is performed twice for one read out.
In the first time, the reset levels (P-phase) of the unit pixels 21 are read out to the vertical signal lines 8 (−1 to −n) and AD conversion is performed.
Variation is included in the reset level P-phase of each pixel.
In the second time, signals photoelectrically converted by each of the unit pixels 21 are read out (D-phase) to the vertical signal lines 8 (−1 to −n) and AD conversion is performed.
Since there is also variation in the D-phase of each pixel, by performing (D-phase level-P-phase level), it is possible to realize correlated double sampling (CDS).
A signal converted to a digital signal is recorded in the counter latch 51-2, is read out in order to the amplifier circuit 7 via the horizontal transfer line 9 by the horizontal (column) transfer scanning circuit 4 in order, and is finally output.
In this manner, the column parallel output processing is performed.
As described above, in a solid-state imaging element of a voltage slope method which performs general column parallel read out, the standard clock CK which decides AD resolution is input to a ripple counter arranged for all of the column lines, and a count operation is performed for each column.
As a result, if clock frequency increases and the number of horizontal columns becomes large, power consumed by the counter of each column increases, and if the product characteristics deteriorate, there are adverse effects such as a fall in operation margins due to IR drop and the like at the same time.
Additionally, due to a large burden on a standard clock line, degrading of clock duty becomes larger as the standard clock becomes faster and there is a limit on AD resolution.
It is desirable to provide a column A/D converter, a column A/D conversion method, a solid-state imaging element, and a camera system that are capable of significantly reducing power consumption.